1. Field of the Invention
The present invention relates to an array substrate for a fringe field switching (FFS) mode liquid crystal display (LCD) device and more particularly to an array substrate for an FFS mode LCD device being capable of minimizing a parasitic capacitance between a pixel electrode and a data line and a method of fabricating the array substrate being capable of reducing production costs.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and the TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode to have excellent properties of transmittance and aperture ratio. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.
An in-plane switching (IPS) mode LCD device may be used to resolve the above-mentioned limitations. FIG. 1 is a cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the array substrate and the color filter substrate are separated and face each other. The array substrate includes a first substrate 10, a common electrode 17 and a pixel electrode 30. Though not shown, the array substrate may include a TFT, a gate line, a data line, and so on. The color filter substrate includes a second substrate 9, a color filter layer (not shown), and so on. A liquid crystal layer 11 is interposed between the first substrate 10 and the second substrate 9. Since the common electrode 17 and the pixel electrode 30 are formed on the first substrate 10 on the same level, a horizontal electric field “L” is generated between the common and pixel electrodes 17 and 30.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions of an IPS mode LCD device according to the related art. As shown in FIG. 2A, when the voltage is applied to the IPS mode LCD device, liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 are unchanged. But, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules are arranged by the horizontal electric field, the IPS mode LCD device has a characteristic of a wide viewing angle. FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not generated between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 is not changed.
A fringe field switching (FFS) mode LCD device having additional advantages has been introduced. FIG. 3 is a plane view showing one pixel region of an array substrate for an FFS mode LCD device according to the related art, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3.
Referring to FIGS. 3 and 4, a gate line 60 is formed along a first direction on a substrate 51 of an array substrate 50, and a data line 70 along a second direction cross the gate line 60 to define a pixel region P. A thin film transistor (TFT) Tr, which includes a gate electrode 62, a gate insulating layer 64, a semiconductor layer 66, a source electrode 72 and a drain electrode 74, is formed at a crossing portion of the gate and data lines 60 and 70. The TFT Tr is disposed in a switching region TrA defined in the pixel region P. The TFT Tr is connected to the gate and data lines 60 and 70. Namely, the gate electrode 62 is connected to the gate line 60, and the source electrode 72 is connected to the data line 70. The semiconductor layer 66 includes an active layer 66a of intrinsic amorphous silicon and an ohmic contact layer 66b of impurity-doped amorphous silicon.
In addition, a pixel electrode 76, which is connected to the drain electrode 74 of the TFT Tr, is formed in the pixel region P. A passivation layer 80 as an insulating layer is disposed on the pixel electrode 76 and the TFT Tr. A common electrode 90 having a plate shape is disposed on the passivation layer 80. The common electrode 90 includes a plurality of holes 92 of a slit shape. The holes 92 overlap the pixel electrode 76. The pixel electrode 76 covers the pixel region P, and the common electrode 90 covers an entire surface of the substrate 51.
With voltages to the pixel electrode 76 and the common electrode 90, a fringe field is generated between the pixel and common electrodes 76 and 90 such that liquid crystal molecules are driven by the fringe field.
As shown in FIG. 4, in the related art FFS mode LCD device, the pixel electrode 76 is positioned to be closer to the data line 70 such that a parasitic capacitance is generated between the pixel electrode 76 and the data line 70. Problems, i.e, a flicker phenomenon, are generated by the parasitic capacitance. Particularly, when a size of the pixel electrode 76 is increased to improve an aperture ratio, the problems are serious because a distance between the pixel electrode 76 and the data line 70 is further decreased.